1. Field of the Invention
This invention relates generally to semiconductor devices, and, more particularly, to determining cell-based timing elements from a transistor-level design for a semiconductor device.
2. Description of the Related Art
Modern integrated circuits, including processors, memory elements, application-specific integrated circuits, and the like, typically include tens of thousands of individual transistors. The precise number of transistors, as well as the interconnections between the transistors and/or other elements of the integrated circuit, may be specified in a circuit design. In principle, circuit designs could be tested by fabricating a device based on the circuit design and then directly testing the device to make sure that it performs in the expected manner. However, configuring a semiconductor fabrication facility to fabricate the device and then fabricating one or more devices for testing would cost them in desirably large amount of time and/or money. Accordingly, circuit designs are typically tested by simulating the timing of the circuit design.
One technique for simulating a circuit design is to determine the circuit timing by simulating the interaction of individual transistors in the circuit. The most popular program for transistor-level simulation is the Simulation Program with Integrated Circuit Emphasis) (SPICE), which was developed at Berkeley starting in the 1970s, and is widely available in multiple forms today. Transistor-level simulation programs use a matrix-based technique for determining the circuit timing, which may make the transistor-level approach unwieldy and/or impractical for relatively large circuits, e.g. circuits that have in excess of about 10,000 transistors. Furthermore, transistor-level simulations typically require that the design engineer specify a particular path through the circuit design, e.g. in the form of a vector, in order to determine the time delay(s) associated with the path. Relatively large circuits may have numerous paths and the design engineer may have difficulty determining the correct path and, in some cases, may analyze an incorrect path. Some faster versions of transistor-level simulations may assume one or more heuristics in order to partition the circuit design.
Alternatively, the circuit design may be specified in terms of one or more cells. A cell-based circuit design specifies the properties of one or more cell elements and the interconnections between the cell elements. For example, the cell elements may include NAND gates, NOR gates, and the like. The cell-based circuit design may then specify the interconnections between the NAND gates and/or the NOR gates that are necessary to implement the logic and/or functions of the desired device. The particular arrangements of transistors that may be used to implement the cell elements are not typically specified by the cell-based circuit design. Instead, the transistor-level implementation is left undefined and design engineers are free to choose from among many possible transistor-level implementations of the cell elements.
Cell-based circuit designs may be simulated using static timing techniques. Static timing is a vectorless technique and so there is no need for the design engineer to specify a timing path through the circuit. Instead, a static timing simulator examines all possible paths through the circuit design. However, static timing cannot be applied directly to a transistor-level circuit design. Some static timing simulators include internal modules that attempt to convert transistor-level circuit designs to cell-based designs by modeling the transistor-level circuit design. However, when compared to cell-based static timing, these approaches typically have a low capacity and low control over the simulation. Furthermore, the models that are employed may impose a number of restrictions on the simulation. For example, the cells are only valid in context in which the cell is used.